1. Field of the Invention
The present invention relates to a liquid crystal display using a horizontal electric field, and more particularly to a liquid crystal display and a fabricating method thereof that are capable of reducing the number of mask processes.
2. Description of the Related Art
Generally, the liquid crystal displays (LCDs) control light transmittance of liquid crystal material using an electric field to thereby display a picture. The liquid crystal displays are classified into a vertical electric field type and a horizontal electric field type in accordance with a direction of the electric field driving the liquid crystal.
The liquid crystal display of vertical electric field type, in which a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate are arranged as facing each other, drives a liquid crystal of a twisted nematic mode (TN) by a vertical electric field formed between the common electrode and the pixel electrode. The liquid crystal display of vertical electric field type has an advantage of a large aperture ratio, while it has a defect of a narrow viewing angle of about 90°.
The liquid crystal display of a horizontal electric field type drives a liquid crystal in an in-plane switching (hereinafter referred to as “IPS”) mode by a horizontal electric field between the pixel electrode and the common electrode disposed in parallel on the lower substrate. The liquid crystal display of horizontal electric field type has an advantage of a wide viewing angle about 160°. Hereinafter, the liquid crystal display of the horizontal electric field type will be described in detail.
The liquid crystal display of the horizontal electric field type comprises a thin film transistor array substrate (a lower substrate) and a color filter array substrate (an upper substrate) facing and joined to each other, a spacer for uniformly maintaining a cell gap between two substrates and a liquid crystal injected into a space provided by the spacer.
The thin film transistor array substrate includes a plurality of signal lines for forming a horizontal electric field on a basis of a pixel, a plurality of thin film transistors, an alignment film applied for a liquid crystal alignment thereon. The color filter array substrate includes a color filter for representing a color, a black matrix for preventing a light leakage and an alignment film applied for a liquid crystal alignment thereon.
In such a liquid crystal display, since the manufacture of a thin film transistor array substrate involves a semiconductor process and requires a plurality of mask processes, the complexity of the manufacturing process is a major factor raising the manufacturing cost of the liquid crystal display panel. In order to solve this, the thin film transistor array substrate has been developed to reduce the number of mask processes. This is because one mask process may include a lot of processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, to name a few. Recently, there has been highlighted a four-step mask process in which one mask process is reduced from the five-step mask process that is employed related art.
FIG. 1 is a plan view illustrating a related art thin film transistor substrate of a horizontal electric type using the four-step mask process, and FIG. 2 is a sectional view of the thin film transistor array substrate taken along the I-II′ and II-II′ line in FIG. 1.
Referring to FIGS. 1 and 2, the related art thin film transistor array substrate of the horizontal electric type comprises a gate line 2 and a data line 4 formed crossing each other on a lower substrate 45, a thin film transistor 6 formed at each crossing, a pixel electrode 14 and a common electrode 18 formed in order to apply the horizontal electric field in a pixel region defined by the interconnection part and a common line 16 connected to the common electrode 18. Further, the related art thin film transistor array substrate comprises a storage capacitor 20 formed at an overlapped portion between the pixel electrode 14 and the common line 16, a gate pad 24 connected to the gate line 2, and a data pad 30 connected to the data line 4 and a common pad 36 connected to the common line 16.
The gate line 2 supplies a gate signal to the gate electrode 8 of the thin film transistor 6. The data line 4 supplies a pixel signal to the pixel electrode 14 via a drain electrode 12 of the thin film transistor 6. The gate line 2 and the data line 4 are formed in an intersection structure to thereby define the pixel region 5.
The common line 16 is formed in parallel with the gate line 2 with the pixel region 5 positioned between the common line 16 and the gate line 2 to supply a reference voltage for driving the liquid crystal to the common electrode 18.
The thin film transistor 6 responds to the gate signal of the gate line 2 so that the pixel signal of the data line 4 is charged to the pixel electrode 14. To this end, the thin film transistor 6 comprises a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4 and a drain electrode 12 connected to the pixel electrode 14. Further, the thin film transistor 6 includes an active layer 48 overlapping with the gate electrode 8 with a gate insulating film 46 positioned between the thin film transistor 6 and the gate electrode 8 and defining a channel between the source electrode 10 and the drain electrode 12. The active layer 48 is formed to overlap with the data line 4, a data pad lower electrode 32 and a storage electrode 22. On the active layer 48, an ohmic contact layer 50 making an ohmic contact with the data line 4, the source electrode 10, the drain electrode 12, the data pad lower electrode 32 and the storage electrode 22 is further formed.
The pixel electrode 14, which is connected to the drain electrode 12 of the thin film transistor 6 via a first contact hole 13 passing through a passivation film 52, is formed in the pixel region 5. In particular, the pixel electrode 14 comprises a first horizontal part 14A connected to the drain electrode 12 and formed in parallel with adjacent gate line 2 and a second horizontal part 14B formed to overlap with the common line 16 and a finger part 14C formed in parallel with the common electrode 18.
The common electrode 18 is connected to the common line 16 and is formed in the pixel region 5. In addition, the common electrode 18 is formed in parallel with the finger part 14C of the pixel electrode 14 in the pixel region 5.
Accordingly, a horizontal electric field is formed between the pixel electrode 14 to which the pixel signal is supplied via the thin film transistor 6 and the common electrode 18 to which the reference voltage is supplied via the common line 16. Moreover, the horizontal electric field is formed between the finger part 14C of the pixel electrode 14 and the common electrode 18. The liquid crystal molecules arranged in the horizontal direction between the thin film transistor array substrate and the color filter array substrate by the horizontal electric field rotate due to a dielectric anisotropy. The light transmittance transmitting the pixel region 5 differs according to the amount of rotation of the liquid crystal molecules and thereby the pictures can be produced.
The storage capacitor 20 consists of the common line 16, a storage electrode 22 overlapping with the common line 16, with the gate insulating film 46, the active layer 48 and the ohmic contact layer 50 positioned therebetween, and a pixel electrode 14 connected via a second contact hole 21 passing through the storage electrode 22 and the passivation film 52. The storage capacitor 20 allows a pixel signal charged in the pixel electrode 14 to be stably maintained until the next pixel signal is charged.
The gate line 2 is connected, via the gate pad 24, to a gate driver (not shown). The gate pad 24 consists of a gate pad lower electrode 26 extending from the gate line 2, and a gate pad upper electrode 28 connected to the gate pad lower electrode 26 via a third contact hole 27 passing through the gate insulating film 46 and the passivation film 52.
The data line 4 is connected, via the data pad 30, to the data driver (not shown). The data pad 30 consists of a data pad lower electrode 32 extended from the data line 4, and a data pad upper electrode 34 connected, via a fourth contact hole 33 passing through the passivation film 52, to the data pad lower electrode 32.
The common line 16 is supplied with the reference voltage from the exterior reference voltage source (not shown) via the common pad 36. The common pad 36 consists of a common pad lower electrode 38 extended from the common line 16, and a common pad upper electrode 40 connected, via a fifth contact hole 39 passing through the gate insulating film 46 and the passivation film 52, to the common pad lower electrode 38.
A method of fabricating the thin film transistor substrate having the above-mentioned structure using the four-step mask process will be described in detail with reference to FIGS. 3A to 3D.
Referring to FIG. 3A, a first conductive pattern group including the gate line 2, the gate electrode 8 and the gate pad lower electrode 26 is formed on the lower substrate 45 using the first mask process.
More specifically, a first metal layer 42 and a second metal layer 44 are sequentially formed on the upper substrate 45 by a deposition technique such as sputtering to form a gate metal layer of double-structure. Then, the gate metal layer is patterned by the photolithography and the etching process using a first mask to thereby form the first conductive pattern group including the gate line 2, the gate electrode 8, the gate pad lower electrode 26, the common line 16, common electrode 18 and the common pad lower electrode 38. Herein, the first metal layer 42 is formed with an aluminum system metal and the second metal layer 44 is formed with chrome (Cr) or molybdenum (Mo).
Referring to FIG. 3B, the gate insulating film 46 is formed on the lower substrate 45 provided with the first conductive pattern group. Further, a semiconductor pattern group including the active layer 48 and the ohmic contact layer 50 and a second conductive pattern group including the data line 4, the source electrode 10, the drain electrode 12, the data pad lower electrode 32 and the storage electrode 22 are formed on the gate insulating film 46 using the second mask process.
More specifically, the gate insulating film 46, a first semiconductor layer, a second semiconductor layer and a data metal layer are sequentially formed on the lower substrate 45 provided with the first conductive pattern group by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and the sputtering, etc. Herein, the gate insulating film 46 is made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). The first semiconductor layer is made of undoped amorphous silicon and the second conductor layer is made of amorphous silicon doped with an impurity of a N type or P type. The data metal layer is made of molybdenum (Mo), titanium (Ti), tantalum (Ta) or molybdenum alloy, etc.
A photo-resist pattern is formed on the data metal layer by the photolithography using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other photo-resist patterns of region portions.
Subsequently, the data metal layer is patterned by a wet etching process using the other photo-resist patterns to thereby provide the data pattern that included the data line 4, the source electrode 10, the drain electrode 12 being integral to the source electrode 10 and the storage electrode 22.
Next, the first semiconductor layer and the second semiconductor layer are patterned at the same time by a dry etching process using the same photo-resist pattern to thereby provide the ohmic contact layer 50 and the active layer 48.
The photo-resist pattern having a relatively low height is removed from the channel portion by the ashing process and thereafter the source electrode, the drain electrode and the ohmic contact layer 50 of the channel portion are etched by the dry etching process. Thus, the active layer 48 of the channel portion is exposed to separate the source electrode 10 from the drain electrode 12.
A remainder of the photo-resist pattern on the second conductive pattern group is removed using the stripping process.
Referring to FIG. 3C, the passivation film 52 including first to fifth contact holes 13, 21, 27, 33 and 39 are formed on the gate insulating film 46 provided with the second conductive pattern group using the third mask process.
More specifically, the passivation film 52 is entirely formed on the gate insulating film 46 provided with the data pattern by a deposition technique such as the plasma enhanced chemical vapor deposition (PECVD). The passivation film 52 is patterned by the photolithography and the etching process using the third mask to thereby form first to fifth contact holes 13, 21, 27, 33 and 39. The first contact hole 13 is formed in such a manner as to pass through the passivation film 52 and expose the drain electrode 12, whereas the second contact hole 21 is formed in such a manner as to pass through the passivation film 52 and expose the storage electrode 22. The third contact hole 27 is formed in such a manner as to pass through the passivation film 52 and the gate insulating film 46 and expose the gate pad lower electrode 26. The fourth contact hole 33 is formed in such a manner as to pass through the passsivation film 52 and exposes the data pad lower electrode 32. The fifth contact hole 39 is formed in such a manner as to pass through the passivation film 52 and the gate insulating film 46 and expose the common pad lower electrode 38. Herein, when a metal which has high ratio of dry etching like molybdenum (Mo) is used for the data metal, the first contact hole 13, the second contact hole 21 and the forth contact hole 33 are formed in such a manner as to pass through to the drain electrode 12, the storage electrode 22 and the data pad lower electrode 32, respectively, to thereby expose their side.
The passivation film 52 is made of an inorganic insulating material such as the gate insulating film 46 or an organic insulating material having a small dielectric constant such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.
Referring to FIG. 3D, a third conductive pattern group including the pixel electrode 14, the gate pad upper electrode 28, the data pad upper electrode 34 and the common pad upper electrode 40 is formed on the passivation film 52 using the fourth mask process.
More specifically, a transparent conductive film is coated onto the passivation film 52 by a deposition technique such as sputtering, etc. Then, the transparent conductive film is patterned by the photolithography and the etching process using a fourth mask, to thereby provide the third conductive pattern group including the pixel electrode 14, the gate pad upper electrode 28, the data pad upper electrode 34 and the common pad upper electrode 40. The pixel electrode 14 is electrically connected, via the first contact hole 13, to the drain electrode 12 while being electrically connected, via the second contact hole 21, to the storage electrode 22. The gate pad upper electrode 28 is electrically connected, via the third contact hole 37, to the gate pad lower electrode 26. The data pad upper electrode 34 is electrically connected, via the fourth contact hole 33, to the data pad lower electrode 32. The common pad upper electrode 40 is electrically connected, via the fifth contact hole 39, to the common pad lower electrode 38.
In this connection, the transparent conductive film may be made of indium-tin-oxide (ITO), tin-oxide (TO), indium-zinc-oxide (IZO) or indium tin zinc oxide (ITZO).
As described above, the related art thin film transistor array substrate of the horizontal electric field type and the manufacturing method thereof adopts a four-round mask process, thereby reducing the number of manufacturing processes in comparison to the five-round mask process and hence reducing a manufacturing cost to that extent. However, since the four-round mask process still has a complex manufacturing process and limited cost reduction an approach is needed that is capable of further simplifying the manufacturing process and further reducing the manufacturing cost.